1. Field of the Invention
This invention relates to digital arithmetic units, and more particularly to methods for sign-extension of constants.
2. Description of the Related Art
Computers performing arithmetic operations on operands are well-known. Operands that are constant and not variable may be supplied to the computer inside the instruction word itself. Since the instruction word is usually of limited length, the constant inside the instruction word is also limited in size. Typically only an 8-bit byte or a 16-bit half-word is supplied as an immediate constant in the instruction word, while the computer is capable of processing 32-bit data operands. Thus the immediate byte or half-word must be extended to the full 32-bit size of the other operands.
Operands and constants are often represented as binary numbers in two's complement format. Two's complement is widely used because any two numbers may be added together or subtracted in a simple adder. Positive numbers are represented simply as the number itself converted to a binary number. However, the magnitude of numbers that may be represented by a particular number of binary bits is reduced so that the uppermost, or most-significant bit, may be used to indicate the sign of the number. This sign bit is typically a "0" for positive numbers and a "1" for negative numbers. Any two positive numbers may be added together, provided the sum is not greater than the largest representable positive number for the particular number of bits. If the sum is too large, then an overflow has occurred and the result is not valid.
A negative number may be generated from a positive number by a 2-step process. First the number is inverted to get the one's complement; each bit in the binary number is inverted. Thus the sign bit will be inverted from a "0" to a "1", indicating a negative number. Second, a "1" is added to the one's complement of the number to get the two's complement result. This addition may require an extra adder, or preferably the carry-in of the main adder in the ALU may simply be set to a "1" to accomplish the second step. Thus the one's complement of the number is inputted to the ALU together with a second operand, and the carry-in bit of the ALU adds "1" to the result.
When a signed 8-bit constant is added to a 32-bit operand, the constant must normally be sign-extended to 32-bits. The most-significant bit (MSB) of the constant is taken to be its sign bit. This MSB is copied to all 24 extended bit positions to make a 32-bit sign-extended constant. The new sign bit is the new MSB, or the 32nd bit. Thus a positive 8-bit constant will have all zeros in bits 31 to 8, while a negative 8-bit constant will have all ones from bits 31 to 8, and in bit 7, the MSB of the 8-bit constant. A 16-bit constant, or any other size constant may similarly be sign-extended to any larger size.
Often an explicit instruction is used to sign-extend a constant. This may require an additional processor clock. An operand may be sign-extended when being loaded from memory into the Central Processing Unit's (CPU's) registers. However, if the constant is immediate, present in the instruction word itself, then there may not be time to first load this constant into the register file before being inputted into the arithmetic-logic-unit (ALU) for execution. Sign-extension has to be explicitly controlled by the instruction or the ALU may have to be modified to handle sign-extension.
What is desired is a method to sign-extend immediate constants in instruction words without having to explicitly perform a sign-extension operation or instruction. The method must be high-speed but not burden the programmer down with explicit sign-extension.